Energy- and size-efficient ultra-fast plasmonic circuits for neuromorphic computing architectures
Energy- and size-efficient ultra-fast plasmonic circuits for neuromorphic computing architectures
Energy- and size-efficient ultra-fast plasmonic circuits for neuromorphic computing architectures

Objectives

  1. Deploy a new class of ultra-small and low-energy CMOS-compatible plasmonic electro-optic and thermo-optic waveguide platforms
  2. Develop 100 Gb/s ultra-compact plasmonic modulators on SiN for on-chip E/O signal conversion and activation in neuromorphic circuit layouts
  3. Deploy ultra-compact, low-energy and CMOS-manufacturable plasmonic computation devices for neuromorphic weighting
  4. Deploy a powerful 3D cointegrated plasmo-electro-photonic neuromorphic circuit technology
  5. Deploy ultra-compact and energy-efficient programmable linear plasmonic neurons
  6. Deploy ultra-fast plasmo-electronic and nanophotonic activation functions
  7. Experimentally validate plasmo-electronic and plasmo-photonic neurons in feed-forward and recurrent inference applications
  8. Develop training models for neuromorphic plasmonic circuits and evaluate their performance in real DataCenter IT security-oriented applications
  9. Generate a neuromorphic plasmonic circuit software design library for lowering the access barriers of PlasmoniAC technology and validating its use in Deep Learning architectures
The PlasmoniAC project is an initiative of the Photonics Public Private Partnership and has received funding from the European Union's Horizon 2020 Research and Innovation Programme under Grant Agreement No. 871391.
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